In integrated circuits, power consumption and management of power is a critical issue. The reduction of power consumption has become and continues to be increasingly important as more devices are manufactured for battery use, such as portable devices. In the prior art, the use of voltage scaling to reduce power consumption is practiced. Voltage scaling reduces the supply voltage level to portions of an integrated circuit. Often power management techniques are incorporated that detect time periods when a portion of the circuit is less active, or idle, and the power supply to that portion may be reduced. Various phrases describing voltage scaling are used. Dynamic voltage scaling (DVS), adaptive voltage scaling (AVS) and module level voltage scaling (MLVS) are all described in the literature relating to integrated circuits.
A problem that inherently arises when supply voltage level scaling is used in an integrated circuit is cross power domain clock skew. That is, when a clock signal is used in two power domains, and one of them has a voltage supply that changes due to voltage scaling, an increase in clock skew will typically occur. The design used to implement the circuit therefore must be performed with such tolerances that the clock skew does not create erroneous operation. As is known, if a set up time requirement for a data register is violated, or a hold time requirement is violated, the register may not function correctly. Metastable or oscillating operation may occur, or a register may erroneously “flash through” passing data to the output in the wrong clock cycle.
FIG. 1 depicts, as a simplified example, registers and a clock tree for two portions or domains within a single integrated circuit of the prior art. In FIG. 1, a circuit is shown receiving a clock signal labeled CK into two power domain regions, power domain 1 (labeled “PD1”) and power domain 2 (labeled “PD2”). In PD1, a clock tree circuit 10 comprised of a plurality of parallel buffer circuits 11 is shown. As is known in the art, a clock tree is used to fan out a heavily loaded clock signal to various registers or loads so that each load receives a rising and falling edge of the signal CK at very close to the same time, so that the circuitry may correctly latch and hold data inputs as Q outputs of synchronous registers in the circuit. A typical register 13 is shown receiving a clock pulse CP1 in PD1. Similarly, power domain PD2 is subject to voltage scaling and comprises a clock tree 15 of buffers 17 which receive the clock pulse CK and fan out the local clock signals. Register 19 receives a clock pulse CP2. Register 19 is coupled to register 13 in PD1, thus the registers communicate across the two power domains. PD1 is not subject to supply voltage scaling; however, PD2 is subject to supply voltage scaling.
FIG. 2 depicts a typical timing diagram for clock pulses CP1 and CP2 when the supply voltages for PD1 and PD2 are the same. In FIG. 2, no difference in time is apparent at the rising edge of CP1 and CP2, that is, there is no clock skew between the domains PD1 and PD2. In contrast, in FIG. 3, the effect of voltage scaling in PD2 is shown. The timing diagram of FIG. 3 shows the relative timing of the rising edges of CP1 and CP2 when the voltage scaling is in effect. In FIG. 3, there is a time difference between the rising edges, and clock skew is occurring. As the supply voltage to the circuitry in PD2 is reduced, the time delays increase and thus, CP2 arrives later in time to register 19 than CP1 arrives to register 13. If this skew increases to a large skew (in time), erroneous operation of the two registers may occur.
A continuing need thus exists for an improved clock skew compensation circuit and methods that provide for robust operation of the clocked circuits across power domains even when voltage scaling is applied to a portion of the circuitry.